To maintain the efficient use of time in high speed electronic circuitry, it is essential to provide clocking signals that are accurately related to each other in time. As the number of components in such a system increases, the number of clock logic components needed for that system also increases, so that accurate clocking becomes more difficult due to the additive effect of clock logic time variations. To deal with this problem, most present designs utilize a balanced tree or other carefully controlled interconnection pattern. However, the variability of timing across these patterns inevitably increases indefinitely with the size of the system.
One approach to this problem is proposed in U.S. Pat. No. 5,163,068 issued Nov. 10, 1992 for "Arbitrarily Large Clock Networks with Constant Skew Bound" by Ahmed El-Amawy, which patent is hereby incorporated by reference herein. In the El-Amawy patent, global synchronization of an arbitrarily large computing structure is sought such that the clock skew between any two communicating cells of that structure would be bounded by a constant, regardless of the size of the computing structure. El-Amawy proposes using clock nodes to perform simple processing on clock signals. Each such clock signal would be processed in a manner similar to that in which data signals would be processed by that system. A cyclic network of the clock nodes, within certain topological constraints, along with timing constraints on the function of the clock nodes, is proposed to maintain a constant bound on the clock skew between those nodes. The inputs to each clock node would be combined to produce a single output signal, which in turn would then be sent to data-processing cells associated with that node and to neighboring clock nodes. The first arriving input from a given clocking event would trigger that node's action, resulting in an output pulse. Further information about the El-Amawy approach is described in Ahmed El-Amawy, "Clocking Arbitrarily Large Computing Structures Under Constant Skew Bound" in IEEE Transactions on Parallel and Distributed Systems, Vol. 4, No. 3, March 1993, pages 241-255, which is hereby incorporated herein by reference.
The El-Amawy patent asserts that only the directly interconnected portions of a clock system need be controlled in time, and proposes a clocking approach that was intended to allow a constant time bound to be maintained across all such portions. However, in high speed logic, the clocks must be more accurately timed than El-Amawy's approach can provide, because the El-Amawy approach is limited by the distance between the interconnected parts and by the delays through the logic parts employed.
The El-Amawy patent provides a clocking system whose clock time-skew bound will fall within a certain tolerance. In other words, there will be a plurality of clocks whose respective phases will fall within a certain tolerance (in nanoseconds) of each other. That tolerance is at least 2 .DELTA., where .DELTA. is the sum of the maximum signal delays through one wire connection and one set of clock logic for his clocking system. These delays must be large enough to provide for intrinsic logic delays and signal propagation at the speed of light. However, because these delays must be so large, the accuracy of the El-Amawy approach is limited by this delay. In systems that use fast clocks, this delay is a significant portion of the clock period, causing a corresponding loss of available logic computation time. The El-Amawy patent also shows how to reduce the total amount of clock logic needed by increasing the multiple of .DELTA. and, consequently, increasing the clock skew.
In systems having large numbers of synchronized clocks, clock fanout logic permits errors between clocks to grow without bound as system size increases. The El-Amawy patent reduces such errors but allows too large a skew bound between clock circuits. If phase locked loops were instead used to control clock skew, they would introduce undesirable coupled oscillation behavior that would be hard to control.
El-Amawy states that he provides a bounded skew, such that no connected components suffer clock skew greater than n.DELTA., where the number of nodes n is greater than 1, and .DELTA. is the sum of the worst case node and link propagation delays. Although bounded skew is quite desirable, the El-Amawy value for skew is much too large. Addition of phase locked loops to attempt to control skew may not work, but would introduce further problems. Phase locked loops have substantial costs in terms of their power requirements and chip area requirements, and furthermore have at least questionable stability in a scalable environment.